Integrated circuit image sensors are widely used for capturing images in a variety of applications, such as digital cameras, camcorders, printers, scanners, etc. Integrated circuit image sensors generally include a plurality of photoelectric conversion elements that capture optical information and convert the optical information into electrical signals. A plurality of logic circuits is also included, which can be used to control the photoelectric conversion elements and to process the electrical signals that are produced by the photoelectric conversion elements.
The photoelectric conversion elements may be included in a pixel region in an image sensor integrated circuit substrate. A given photoelectric conversion pixel may include a single photodiode and four read transistors, commonly referred to as a transfer transistor, a reset transistor, a select transistor and a driver transistor. The logic circuits may be included in a logic region of the image sensor integrated circuit substrate. The logic region may include a timing generator, row/column decoders, a row driver, a correlated double sampler, an analog-to-digital converter, latches and/or other logic circuits.
There are two types of image sensor technologies that are presently widely used: a Charge Coupled Device (CCD) and a CMOS Image Sensor (CIS). CMOS Image Sensors may be increasingly used due to their potential for relatively high speed operation at relatively low power.
FIG. 1 is a block diagram of a conventional CMOS image sensor and its operating environment. Referring to FIG. 1, the CMOS image sensor includes a CMOS image sensor integrated circuit substrate 110. An Active Pixel Sensor (APS) array 112 is included in the integrated circuit substrate 110. The APS array 112 includes a two-dimensional array of photoelectric conversion elements, such as photodiodes, that are configured to capture optical information concerning an object 140 that may be provided via an optical system, such as a lens 142. A timing generator 128 generates timing signals for reading the APS array 112. A row driver 114 selects a pixel. A Corrected Double Sampling (CDS) unit 116 provides corrected double sampling of the output signal of a selected pixel. A comparator 118 compares the CDS output with a reference signal, and an Analog-To-Digital Converter (ADC) 122 converts the analog signal from the comparator 118 to a digital signal. A control register 132 controls the timing generator 128, a ramp generator 126 that drives the comparator 118 and a buffer 124 that stores the output of the ADC 122 to produce image data.
Still continuing with the description of FIG. 1, a digital signal processor (DSP) 150 may include an external interface 152, a camera control 154 and an image signal processor 156. The DSP 150 drives an external display 158. It will be understood that the DSP 150 may be embodied as a separate integrated circuit substrate or may be at least partially integrated with the image sensor integrated circuit substrate 110.
The design and operation of a CMOS image sensor, as illustrated in FIG. 1, are well known to those having skill in the art and need not be described further herein. Moreover, it will be understood that an image sensor need not include every block described in FIG. 1, that the functionality of a given block of FIG. 1 may be separated into two or more blocks, and that the functionality of two or more blocks of FIG. 1 may be merged.
As noted above, the image sensor integrated circuit substrate 110 may be divided into a pixel region that may include the APS array 112 and associated transfer, select, driver and reset transistors that may be used to access the photoelectric conversion elements in the APS array 112. Moreover, the logic region may include the timing generator 128, the row driver 114, the corrected double sampler 116, the comparator 118, the analog-to-digital converter 122, the buffer 124 and other circuits, such as row/column decoders, not shown in FIG. 1. As is also well known to those having skill in the art, the CMOS devices in the pixel region and the logic region may include P-channel devices, commonly referred to as PMOS devices, and N-channel devices, commonly referred to as NMOS devices. Moreover, an isolation layer also may be provided in the image sensor integrated circuit substrate, to define the active regions and to isolate the various devices from one another.
As is also well known to those having skill in the art, image sensors may suffer from a phenomenon known as “dark current”. Dark current refers to electric charge that accumulates in the image sensor photodiodes in the absence of light. Dark current may manifest itself as an erroneous white pixel in the image. As is also well known to those having skill in the art, dark current may be caused by silicon dangling bonds, plasma damage, stress, implant damage, wafer defects, undesired electric fields and/or many other phenomena that may arise in the fabrication of an image sensor. These phenomena may generate some charge in the photodiodes, even in the absence of incident light.
It is also known that some dark current may result from the Shallow Trench Isolation (STI) methods and structures that are used in the image sensor. STI methods/structures may be used to form isolation regions that define the active regions and isolate the various devices from one another. In particular, it is known that the STI trench walls may have damage that is caused by anisotropic etching or dry etching processes that are used in fabricating the trenches. Etching damage, such as dangling bonds and/or stacking faults, may contribute to dark current.
One technique for reducing dark current in CMOS image sensors is described in U.S. Pat. No. 6,888,214 to Mouli et al., entitled Isolation Techniques for Reducing Dark Current in CMOS Image Sensors. As stated in the Abstract of this patent, this patent provides isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.
Another isolation technique for a CMOS image sensor is described in Korean Patent Publication No. 10-2004-0065335, published Jul. 22, 2004, entitled Method for Manufacturing CMOS Image Sensor. As stated in the extended English Abstract of this published Korean application, a method for manufacturing a CMOS image sensor is provided to reduce cross talk and leakage current by forming a channel stop ion-implanted region using a self-aligned mask. A buffer oxide layer, a pad nitride layer, and an Anti-Reflective Coating (ARC) layer are stacked on a substrate. The first photoresist pattern with the first opening part is formed on the resultant structure. The stacked structure is etched to expose the substrate. A trench is formed by selectively etching the exposed substrate. The second photoresist pattern with the second opening part is formed on the first photoresist pattern, wherein the second opening part is wider than that of the first opening part. A channel stop ion-implanted region is then formed in the substrate.